garden of eda

logisim-evolution

logisim-evolution

An educational logic circuit designer and simulator with a graphical interface, derived from the original Logisim project. Used widely in digital logic courses.

chisel

chipsalliance

Chisel: A Modern Hardware Design Language

yosys

YosysHQ

This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

rocket-chip

chipsalliance

This repository contains the Rocket chip generator necessary to instantiate the RISC-V Rocket Core. For more information on Rocket Chip, please consult our technical report.

verilator

verilator

Verilator open-source SystemVerilog simulator and lint system

skywater-pdk

google

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

iverilog

steveicarus

1. What is ICARUS Verilog? 2. Building/Installing Icarus Verilog From Source - Compile Time Prerequisites - Compilation - (Optional) Testing - Installation 3. How Icarus Verilog Works - Preprocessing - Parse - Elaboration - Optimization - Code Generation - Attributes 4.

OpenROAD

The-OpenROAD-Project

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

ghdl

ghdl

This directory contains the sources of GHDL, the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL).

cocotb

cocotb

cocotb: Python-based chip (RTL) verification

chipyard

ucb-bar

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

riscv-boom

riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

amaranth

amaranth-lang

A modern hardware definition language and toolchain based on Python

SpinalHDL

SpinalHDL

- A language to describe digital hardware - Compatible with EDA tools, as it generates VHDL/Verilog files - Much more powerful than VHDL, Verilog, and SystemVerilog in its syntax and features - Much less verbose than VHDL, Verilog, and SystemVerilog - Not an HLS, nor based on…

verible

chipsalliance

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

OpenLane

The-OpenROAD-Project

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

nextpnr

YosysHQ

nextpnr portable FPGA place and route tool

xls

google

Docs | Quick Start [](https://bit.ly/learn-xls) | Tutorials

fusesoc

olofk

Package manager and build abstraction tool for FPGA/ASIC development

VeriGPU

hughperkins

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

wireguard-fpga

chili-chips-ba

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

vtr-verilog-to-routing

verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

abc

berkeley-abc

ABC: System for Sequential Logic Synthesis and Formal Verification

siliconcompiler

siliconcompiler

SiliconCompiler is a modular hardware build system ("make for silicon"). The project philosophy is to "make the complex possible while keeping the simple simple".

metroboy

aappleby

A repository of gate-level simulators and tools for the original Game Boy.

slang

MikePopoloski

SystemVerilog compiler and language services

gtkwave

gtkwave

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

apio

FPGAwars

:seedling: Open source ecosystem for open FPGA boards

veryl

veryl-lang

Veryl: A Modern Hardware Description Language

Cores-VeeR-EH1

chipsalliance

This repository contains the VeeR EH1 design RTL.

nvc

nickg

NVC supports almost all of VHDL-2008 with the exception of PSL, and it has been successfully used to simulate several real-world designs. Experimental support for Verilog and VHDL-2019 is under development.

vunit

VUnit

VUnit is a unit testing framework for VHDL/SystemVerilog

edalize

olofk

An abstraction library for interfacing EDA tools

PipelineC

JulianKemmerer

PypelineC: A hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

OpenTimer

OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

riscv_vhdl

sergeykhbr

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

OpenROAD-flow-scripts

The-OpenROAD-Project

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

basejump_stl

bespoke-silicon-group

BaseJump STL: A Standard Template Library for SystemVerilog

awesome-open-hardware-verification

ben-marshall

A List of Free and Open Source Hardware Verification Tools and Frameworks

calyx

calyxir

Intermediate Language (IL) for Hardware Accelerator Generators

OpenSTA

The-OpenROAD-Project

OpenSTA is a gate level static timing verifier. As a stand-alone executable it can be used to verify the timing of a design using standard file formats.

dace

spcl

DaCe - Data Centric Parallel Programming

qkeras

google

QKeras: a quantization deep learning library for Tensorflow Keras

svls

dalance

Download from release page, and extract to the directory in PATH.

sby

YosysHQ

SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

rust_hdl

VHDL-LS

A fast VHDL language server and analysis library written in Rust

librelane

librelane

ASIC implementation flow infrastructure, successor to OpenLane

sv-parser

dalance

SystemVerilog parser library fully compliant with IEEE 1800-2017

surf

slaclab

A huge VHDL library for FPGA and digital ASIC development

async_fifo

dpretet

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

rggen

rggen

Code generation tool for control and status registers

pymtl3

pymtl

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

verilog-eval

NVlabs

Verilog evaluation benchmark for large language model

f4pga

chipsalliance

This is the top-level repository for the F4PGA project, which is a Workgroup under the CHIPS Alliance; consisting of members from different backgrounds, including FPGA vendors, industrial users and academia (see Documentation > Community); who collaborate to build a more open…

caravel

efabless

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

allo

cornell-zhang

Allo Accelerator Design and Programming Framework (PLDI'24)

svlint

dalance

SystemVerilog linter compliant with IEEE1800-2017. Written in Rust, based on sv-parser. Svlint is also integrated with most text editors via svls.

gemm_hls

spcl

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

forth-cpu

howerj

A Forth CPU and System on a Chip, based on the J1, written in VHDL

nngen

NNgen

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

Systolic-array-implementation-in-RTL-for-TPU

abdelazeem201

IC implementation of Systolic Array for TPU

openlane2

chipfoundry

The next generation of OpenLane, rewritten from scratch with a modular architecture

vaporview

Lramseyer

Vaporview is an open source waveform viewer extension for VScode.

PandA-bambu

ferrandi

The primary objective of the PandA project is to develop a usable framework that will enable the research of new ideas in the HW-SW Co-Design field.

hlslib

definelicht

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

Cores-VeeR-EL2

chipsalliance

This repository contains the VeeR EL2 RISC-V Core design RTL.

VeeRwolf

chipsalliance

VeeRwolf is a FuseSoC-based reference platform for the VeeR family of RISC-V cores. Currently, VeeR EH1 and VeeR EL2 are supported. See CPU configuration to learn how to switch between them.

heterocl

cornell-zhang

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)

veriloggen

PyHDI

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

f4pga-arch-defs

f4pga

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

PyRTL

UCSBarchlab

A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.

systemrdl-compiler

SystemRDL

SystemRDL 2.0 language compiler front-end

FABulous

FPGA-Research

An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️

raster-i

raster-gpu

A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L), back-face culling, MSAA anti-aliasing, ordered dithering, etc.

OSVVM

OSVVM

OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

kactus2dev

kactus2

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

axi-crossbar

dpretet

Parametric AXI4 crossbar in SystemVerilog

eurorack-pmod

apfaudio

A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.

constellation

ucb-bar

A Chisel RTL generator for network-on-chip interconnects

hwt

Nic30

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

hdl_checker

suoto

Repurposing existing HDL tools to help writing better code

hdl-modules

hdl-modules

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

RTLLM

hkust-zhiyao

An open-source benchmark for generating design RTL with natural language

lstools-showcase

lsils

Showcase examples for EPFL logic synthesis libraries

open-register-design-tool

Juniper

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

verilog-generator

Eriemon

Agent skill for Verilog-2001 RTL generation and FPGA design workflows.

PeakRDL

SystemRDL

Control and status register code generator toolchain

essent

ucsc-vama

Looking for RepCut (ASPLOS 2023), the parallelized version? Please check the repcut branch!

surfer

surfer-project

Modern Rust-based waveform viewer for VCD/FST files, with web and desktop builds.

openasip

cpc

Open Application-Specific Instruction Set processor tools (OpenASIP)

Fuxi

MaxXSoft

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

wal

ics-jku

WAL enables programmable waveform analysis.

universal_NPU-CNN_accelerator

thousrm

hardware design of universal NPU(CNN accelerator) for various convolution neural network

CHARM

arc-research-lab

CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture

DFFRAM

AUCOHL

Standard Cell Library based Memory Compiler using FF/Latch cells

chiselverify

chiselverify

A dynamic verification library for Chisel.

ice-chips-verilog

TimRudy

IceChips is a library of all common discrete logic devices in Verilog

dahlia

cucapra

Time-sensitive affine types for predictable hardware generation

OpenABC

NYU-MLDA

OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

naja

najaeda

Netlist API (and more) for EDA flow development

pyvsc

fvutils

Python packages providing a library for Verification Stimulus and Coverage

vpm

getinstachip

VPM is a powerful package manager for Verilog projects, currently being piloted at Stanford and UC Berkeley. It's designed to streamline the management, reuse, and communication of IP cores and dependencies in hardware design workflows, significantly accelerating your design…

svlangserver

imc-trading

A language server for systemverilog that has been tested to work with coc.nvim, VSCode, Sublime Text 4, emacs, and Neovim

fpga-tidbits

maltanar

A collection of Chisel hardware generators for small but useful components for FPGA projects.

cocotb-coverage

mciepluc

Functional Coverage and Constrained Randomization Extensions for Cocotb

cgra4ml

KastnerRG

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

LSOracle

lnis-uofu

The Logic Synthesis oracle is a framework developed on the top of EPFL logic synthesis libraries to unlock efficient logic manipulation by using different logic optimizers.To do so, the flow splits a design into different partitions and selects different optimizers for different…

HDLGen

WilsonChen003

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

spydrnet

byuccl

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

toolchain-installer

openXC7

Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7

rIC3

gipsyh

LLM-Assisted Hardware Formal Verification Tool

polyphony

polyphony-dev

Polyphony is Python based High-Level Synthesis compiler.

chiselv

carlosedp

A RISC-V Core (RV32I) written in Chisel HDL

OpenCircuitX

openlab-x

Free, open-source EDA platform for VHDL and Verilog. HDL editor, circuit canvas, RTL viewer, waveform viewer, and FPGA toolchain in one window.

HiSparse

cornell-zhang

High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS

MakerCode_RTLChallenge

Weiyet

Public RTL Question Bank of MakerCode https://makercode.jixiao-ai.com/

vericert

ymherklotz

A formally verified high-level synthesis tool based on CompCert and written in Coq.

fiction

cda-tum

An open-source design automation framework for Field-coupled Nanotechnologies

hdl-registers

hdl-registers

An open-source HDL register code generator fast enough to run in real time.

also

nbulsi

ALSO is based on the EPFL Logic Synthesis Libraries, we aim to exploit advanced logic synthesis tools for both modern FPGA and emerging nanotechnologies.

PoC

VHDL

IP Core Library - Published and maintained by the Open Source VHDL Group

aigverse

marcelwa

A Python library for working with logic networks, synthesis, and optimization.

issie

tomcl

Issie - an intuitive cross-platform hardware design application. https://tomcl.github.io/issie

yosys-f4pga-plugins

chipsalliance

Plugins for Yosys developed as part of the F4PGA project.

fliplot

raczben

HTML based waveform viewer for HDL simulators.

svut

dpretet

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

kepler-formal

keplertech

Kepler-Formal is an equivalence checking tool for digital designs. It operates on Verilog, SystemVerilog, and the Naja interchange format, and supports:

nucleusrv

merledu

NucleusRV (RV32-IMAFC) - A 32-bit 5 staged pipelined risc-v core.

cocotb-bus

cocotb

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

DienTu_TKVM_Documents

Quang-Minh-Phung

Kho tài liệu đi từ nền tảng Điện tử căn bản đến Thiết kế vi mạch, tập trung vào Front-End (RTL/DV). Tích hợp kiến thức bổ trợ cho các hướng công việc khác thuộc chuyên ngành Điện Tử. Biên soạn bởi Minh Ú (Phùng Quang Minh).

workcraft

workcraft

Toolset to capture, simulate, synthesize and verify graph models

vga-playground

TinyTapeout

Playground for VGA projects on Tiny Tapeout

cocotb-vivado

themperek

Limited python / cocotb interface to Xilinx/AMD Vivado simulator.

spade

spade-lang

A Hardware Description Language that doesn't make you want to pull your hair out | read-only mirror of https://gitlab.com/spade-lang/spade/

RTLStructLib

Weiyet

Highly optimized (trying my best), synthesizable data structures module/IP library for hardware design

OpenPhySyn

scale-lab

OpenPhySyn is a physical synthesis optimization kit developed at Brown University SCALE lab as part of the OpenROAD flow.

kitty

lsils

kitty is a C++-17 truth table library. It provides efficient implementations for basic truth table manipulations and various algorithms.

Hog

Hog-CERN

Hog (HDL-on-git) is an open-source tool to manage FPGA projects on git

PeakRDL-html

SystemRDL

Generate address space documentation HTML from compiled SystemRDL input

piel

daquintero

Photonic Integrated ELectronics. Microservices to codesign photonics, electronics, quantum, and more.

tywaves-chisel

rameloni

A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code to values dumped by simulators is now possible thanks to Tywaves!

PeakRDL-uvm

SystemRDL

Generate UVM register model from compiled SystemRDL input

SynthPilot

LNC0831

Talk to your AI. Watch it drive Vivado. — an MCP server for AI-driven FPGA development on Xilinx Vivado.

Design-and-ASIC-Implementation-of-32-Point-FFT-Processor

abdelazeem201

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.

Formal-Verification-With-VC-Formal--Tutorials-and-Examples

Ghonimo

This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our goal is to help both beginners and experienced users understand the principles of formal verification and how to apply them effectively using VC Formal.

apytypes

apytypes

APyTypes - Algorithmic data types for Python

coresmith

facebookexperimental

CoreSmith is a Prompt to GDS Agentic Flow

fvm

fvmformal

A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector (this is a mirror of https://gitlab.com/fvmformal/fvm : you can open issues there)

HDL-FSM-Editor

matthiasschweikart

A tool for modeling FSMs by VHDL or Verilog

firesim-lab

pentarisc

A framework for building and running custom target designs with FireSim.

HDL-SCHEM-Editor

matthiasschweikart

A tool for creating HDL-Schematics and generating VHDL/Verilog

VCD Anon

surfer-project

B-ASIC

da

Toolbox for Python 3 that simplifies design and optimization of signal processing circuits for ASIC or FPGA implementation.