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devs

The people behind open-source EDA.

Developer Projects

OpenROAD full flow
OpenROAD-flow-scripts full flow
OpenSTA static timing
OpenLane full flow

siliconcompiler build tool
OpenROAD full flow
OpenROAD-flow-scripts full flow
yosys synthesis

ghdl simulator
OpenLane full flow
vunit testbench

nvc simulator
iverilog simulator
cocotb testbench
vunit testbench
gtkwave waveform viewer
cocotb-bus testbench

OpenROAD full flow
OpenROAD-flow-scripts full flow
OpenSTA static timing

verilator simulator
gtkwave waveform viewer

abc synthesis

OpenROAD full flow
OpenSTA static timing
OpenROAD-flow-scripts full flow

slang language server

surf hdl framework
FABulous full flow

SpinalHDL hdl framework

vtr-verilog-to-routing full flow

yosys synthesis
sby formal verification

dace hls

metroboy simulator

veryl hdl framework
sv-parser language server
svlint language server
svls language server

workcraft synthesis

yosys synthesis
nextpnr place and route

PandA-bambu hls

siliconcompiler build tool

verible language server
xls hls
OpenROAD full flow
yosys-f4pga-plugins uncategorized
vtr-verilog-to-routing full flow
yosys synthesis
OpenSTA static timing

chipyard hdl framework
riscv-boom hdl framework
rocket-chip hdl framework
constellation hdl framework
chisel hdl framework

hwt simulator

nextpnr place and route
yosys synthesis
f4pga-arch-defs hdl framework
FABulous full flow
vtr-verilog-to-routing full flow
OpenROAD full flow

vtr-verilog-to-routing full flow

veriloggen hls
nngen hls

logisim-evolution simulator

yosys synthesis
nextpnr place and route
sby formal verification
apio full flow
abc synthesis

OpenROAD-flow-scripts full flow
OpenROAD full flow
OpenLane full flow
OpenSTA static timing

Hog build tool

PipelineC hls
wireguard-fpga testbench

OpenROAD full flow
OpenROAD-flow-scripts full flow

surf hdl framework

apio full flow
gtkwave waveform viewer

iverilog simulator

amaranth hdl framework
yosys synthesis
nextpnr place and route

iverilog simulator

calyx hls
dahlia hls

vtr-verilog-to-routing full flow

OpenROAD-flow-scripts full flow
OpenROAD full flow

chipyard hdl framework
riscv-boom hdl framework
rocket-chip hdl framework

cocotb testbench
cocotb-bus testbench
verilator simulator

dace hls

rust_hdl language server
vunit testbench
nvc simulator

dace hls
hlslib hls
gemm_hls hls

f4pga-arch-defs hdl framework
vtr-verilog-to-routing full flow
nextpnr place and route
yosys-f4pga-plugins uncategorized
yosys synthesis

PandA-bambu hls

cocotb testbench
cocotb-bus testbench

chisel hdl framework
rocket-chip hdl framework

xls hls
OpenROAD full flow

rocket-chip hdl framework
chisel hdl framework

siliconcompiler build tool
OpenROAD full flow
OpenROAD-flow-scripts full flow

issie simulator

OpenROAD full flow
OpenROAD-flow-scripts full flow

rocket-chip hdl framework
chisel hdl framework

OpenROAD full flow
OpenROAD-flow-scripts full flow

openasip uncategorized

chisel hdl framework
rocket-chip hdl framework

f4pga-arch-defs hdl framework
vtr-verilog-to-routing full flow
nextpnr place and route
yosys-f4pga-plugins uncategorized

rocket-chip hdl framework
chisel hdl framework
riscv-boom hdl framework

fusesoc build tool
edalize build tool
VeeRwolf build tool
Cores-VeeR-EL2 build tool

riscv_vhdl simulator

hdl-registers uncategorized
hdl-modules uncategorized
vunit testbench

f4pga-arch-defs hdl framework
vtr-verilog-to-routing full flow
verible language server
f4pga full flow
yosys synthesis

OpenROAD full flow
OpenROAD-flow-scripts full flow
OpenSTA static timing

cocotb testbench
cocotb-bus testbench

pymtl3 hdl framework

librelane full flow
openlane2 full flow
OpenLane full flow
DFFRAM uncategorized
OpenROAD full flow
yosys synthesis

f4pga full flow
ghdl simulator
vunit testbench
f4pga-arch-defs hdl framework
verible language server
iverilog simulator
edalize build tool
vtr-verilog-to-routing full flow
gtkwave waveform viewer
verilator simulator
fusesoc build tool
yosys synthesis

logisim-evolution simulator

f4pga-arch-defs hdl framework
Cores-VeeR-EL2 build tool
yosys-f4pga-plugins uncategorized
vtr-verilog-to-routing full flow
nextpnr place and route
yosys synthesis

vericert hls

yosys synthesis
sby formal verification

verilator simulator

spade hdl framework

vtr-verilog-to-routing full flow
siliconcompiler build tool

yosys synthesis
OpenROAD full flow
OpenROAD-flow-scripts full flow
abc synthesis
OpenSTA static timing
slang language server

systemrdl-compiler uncategorized
PeakRDL-html uncategorized
PeakRDL uncategorized
PeakRDL-uvm uncategorized

pygears hdl framework
yosys synthesis

essent hdl framework
rocket-chip hdl framework

apio full flow

naja uncategorized

OpenROAD full flow
OpenROAD-flow-scripts full flow

rocket-chip hdl framework
chipyard hdl framework
chisel hdl framework

basejump_stl ip core

rIC3 formal verification

VeriGPU uncategorized

OpenROAD full flow
OpenROAD-flow-scripts full flow

kactus2dev uncategorized

iverilog simulator

xls hls

yosys synthesis

ghdl simulator
PoC ip core

OpenLane full flow

cocotb testbench
fusesoc build tool
cocotb-bus testbench
edalize build tool
cocotb-coverage testbench
verilator simulator

OpenROAD full flow
OpenROAD-flow-scripts full flow

vtr-verilog-to-routing full flow

rggen uncategorized
veryl hdl framework

OpenROAD-flow-scripts full flow
OpenROAD full flow

siliconcompiler build tool
OpenROAD-flow-scripts full flow

riscv-boom hdl framework
rocket-chip hdl framework

xls hls

vtr-verilog-to-routing full flow

SpinalHDL hdl framework

chisel hdl framework
rocket-chip hdl framework
chipyard hdl framework

pymtl3 hdl framework

forth-cpu simulator

OpenROAD full flow
OpenROAD-flow-scripts full flow

heterocl hls
allo hls

calyx hls
dahlia hls

rocket-chip hdl framework
chisel hdl framework

kactus2dev uncategorized

yosys synthesis
amaranth hdl framework

vtr-verilog-to-routing full flow

apytypes hdl framework
spade hdl framework
cocotb testbench
vunit testbench
nvc simulator
rust_hdl language server

OSVVM testbench

xls hls

surf hdl framework

xls hls
chipyard hdl framework
chisel hdl framework
rocket-chip hdl framework

cocotb testbench
cocotb-bus testbench
edalize build tool
cocotb-coverage testbench

kactus2dev uncategorized

iverilog simulator

xls hls
qkeras uncategorized

yosys synthesis
sby formal verification
abc synthesis

OpenROAD full flow
OpenROAD-flow-scripts full flow
OpenSTA static timing

kitty synthesis
abc synthesis
lstools-showcase synthesis
LSOracle synthesis

dace hls

vaporview waveform viewer

verible language server

polyphony hls

f4pga-arch-defs hdl framework
Cores-VeeR-EL2 build tool
f4pga full flow
yosys-f4pga-plugins uncategorized
edalize build tool
verible language server

HDL-FSM-Editor hdl framework
HDL-SCHEM-Editor hdl framework

OpenPhySyn synthesis
OpenROAD full flow

apio full flow

yosys-f4pga-plugins uncategorized
Cores-VeeR-EL2 build tool
f4pga-arch-defs hdl framework
f4pga full flow

vtr-verilog-to-routing full flow

vunit testbench

nextpnr place and route
sby formal verification

naja uncategorized
OpenROAD-flow-scripts full flow

dahlia hls
calyx hls

PyRTL hdl framework

cocotb testbench
cocotb-bus testbench

OpenROAD full flow
yosys synthesis
OpenSTA static timing
abc synthesis
xls hls

OpenROAD full flow
OpenROAD-flow-scripts full flow

PyRTL hdl framework

OpenROAD-flow-scripts full flow
OpenROAD full flow

fpga-tidbits hdl framework

chisel hdl framework
yosys synthesis
rocket-chip hdl framework

OpenROAD full flow
OpenROAD-flow-scripts full flow

xls hls

vtr-verilog-to-routing full flow

apytypes hdl framework

OpenROAD full flow
yosys synthesis

also synthesis

SpinalHDL hdl framework

vtr-verilog-to-routing full flow

kactus2dev uncategorized

xls hls

vtr-verilog-to-routing full flow
LSOracle synthesis

OpenROAD full flow
OpenROAD-flow-scripts full flow

workcraft synthesis

fiction synthesis
aigverse synthesis

xls hls

OpenROAD full flow
OpenROAD-flow-scripts full flow

vtr-verilog-to-routing full flow
siliconcompiler build tool

rocket-chip hdl framework

iverilog simulator

yosys-f4pga-plugins uncategorized
verilator simulator
yosys synthesis

pymtl3 hdl framework

chisel hdl framework
rocket-chip hdl framework
riscv-boom hdl framework

caravel full flow
OpenLane full flow
librelane full flow
openlane2 full flow

pyvsc testbench
verilator simulator

OpenROAD full flow

OpenROAD full flow
OpenSTA static timing
OpenROAD-flow-scripts full flow

vtr-verilog-to-routing full flow

yosys synthesis
sby formal verification

hdl_checker hdl framework

OpenROAD full flow
OpenROAD-flow-scripts full flow

heterocl hls
allo hls

vtr-verilog-to-routing full flow

Hog build tool

OpenROAD full flow

issie simulator

caravel full flow
OpenLane full flow

vtr-verilog-to-routing full flow

dahlia hls
calyx hls

vtr-verilog-to-routing full flow

Hog build tool

f4pga-arch-defs hdl framework
yosys-f4pga-plugins uncategorized
xls hls
f4pga full flow
vtr-verilog-to-routing full flow
OpenROAD-flow-scripts full flow

siliconcompiler build tool
vtr-verilog-to-routing full flow

cocotb testbench
cocotb-bus testbench
cocotb-vivado testbench
iverilog simulator

riscv-boom hdl framework

cgra4ml uncategorized

pygears hdl framework

verilator simulator
Cores-VeeR-EL2 build tool
yosys-f4pga-plugins uncategorized
OpenROAD full flow

xls hls

gtkwave waveform viewer

chisel hdl framework
chiselv hdl framework

chipyard hdl framework
rocket-chip hdl framework

svut simulator
axi-crossbar uncategorized
async_fifo uncategorized